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cy8c21345 CY8C22345, cy8c22545 psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-43084 rev. *m revised may 23, 2011 features powerful harvard-architecture processor: ? m8c processor speeds up to 24 mhz ? 8 8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 v to 5.25 v operating voltage ? industrial temperature range: -40c to +85c advanced peripherals (psoc ? blocks) ? six analog type ?e? psoc blocks provide: ? single or dual 8-bit adc ? comparators (up to four) ? up to eight digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? one shot, multi shot mode support in timers and pwms ? pwm with deadband support in one digital block ? shift register, crc, and prs modules ? full duplex uart ? multiple spi masters or slaves, variable data length support: 8- to 16-bit ? can be connected to all gpio pins ? complex peripherals by combining blocks ? shift function support for fsk detection ? powerful synchronize feat ure support. analog module operations can be synchronized by digital blocks or external signals. high speed 10-bit sar adc with sample and hold optimized for embedded control precision, programmable clocking: ? internal 5% 24/48 mhz oscillator across the industrial temperature range ? high accuracy 24 mhz with optional 32 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal/external oscillator for watchdog and sleep flexible on-chip memory: ? up to 16 kb flash program st orage 50,000 er ase/write cycles ? up to 1-kb sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash optimized capsense ? resource: ? two idac support up to 640 a source current to replace external resistor ? two dedicated clock resources for capsense: ? csd_clk: 1/2/4/8/16/32/ 128/256 derive from sysclk ? cnt_clk: 1/2/4/8 derive from csd_clk ? dedicated 16-bit timers/counters for capsense scanning ? support dual csd channels simultaneous scanning programmable pin configurations: ? 25 ma sink, 10 ma source on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? up to 38 analog inputs on gpios ? configurable interrupt on all gpios additional system resources: ? i 2 c ? slave, master, and multimaster to 400 khz ? supports hardware addressing feature ? watchdog and sleep timers ? user configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference ? supports rtc block into digital peripheral logic top level block diagram digital system digital block array dbc dbc dcc dcc row 1 dbc dbc dcc dcc row 2 sram 1k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect cpu core (m8c) srom flash 16k macs internal voltage ref. digital clocks por and lvd system resets system resources analog system analog ref analog input muxing(l,r) = port 2 port 1 port 0 analog drivers 10-bit sar adc port 3 port 4 psoc core i 2 c system bus cte cte analog block array cte cte sce sce capsense digital resource [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 2 of 34 contents psoc functional overview .............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 additional system resources ..................................... 4 psoc device characteristics . ..................................... 5 getting started .................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 CY8C22345, cy8c21345 28-pin soic ........ .............. 8 cy8c22545 44-pin tqfp ........................................... 9 registers ......................................................................... 10 register conventions ................................................ 10 register mapping tables .......................................... 10 electrical specifications ................................................ 13 absolute maximum ratings ... .................................... 14 operating temperature ............................................ 14 dc electrical characteristics ..................................... 15 ac electrical characteristics ..................................... 19 packaging information ................................................... 25 thermal impedances ................................................ 26 solder reflow specifications ..................................... 26 ordering information ...................................................... 26 ordering code definitions . ....................................... 26 acronyms ........................................................................ 27 acronyms used ......................................................... 27 reference documents .................................................... 27 document conventions ................................................. 28 units of measure ....................................................... 28 numeric conventions ............ .................................... 28 glossary .......................................................................... 28 document history page ................................................. 33 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions ......................................................... 34 [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 3 of 34 psoc functional overview the psoc family consists of many on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, and programmable interconnects. this architecture enables the user to create customized peripheral conf igurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts and packages. the psoc architecture, shown in figure 1 , consists of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows the combining of all the device resources into a complete custom system. the psoc family can have up to five i/o ports connecting to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio (general purpose i/o). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- processor. the cpu uses an in terrupt controller with 21 vectors, to simplify the programming of real time embedded events. program execution is timed an d protected using the included sleep and watch dog timers (wdt). memory encompasses 16 kb of flash for program storage, 1k bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz imo (internal main oscillator). the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is required, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc), and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with progra mmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing gr eat flexibility in external interfacing. every pin can also generate a system interrupt on high level, low level, and change from last read. digital system the digital system is composed of eight digital psoc blocks. each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram digital peripheral configurations are: pwms (8 to 32-bit) pwms with dead band (8 to 32-bit) counters (8 to 32-bit) timers (8 to 32-bit) uart 8 bit with selectable parity (up to two) spi master and slave (up to two) shift register (1 to 32-bit) i2c slave and master (one available as a system resource) cyclical redundancy checker/generator (8 to 32-bit) irda (up to two) pseudo random sequence generators (8 to 32-bit) the digital blocks may be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fam ily. this provides a choice of system resources for your applic ation. family resources are shown in ta b l e 1 on page 5. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbc00 dbc01 dcc02 dcc03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0 port 4 port 3 dbc00 dbc01 dcc02 dcc03 row 1 row input configuration row output configuration [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 4 of 34 analog system the analog system consists of a 10-bit sar adc and six configurable blocks. the programmable 10-bit sar adc is an optimized adc that can be run up to 200 ksps with 1.5 lsb dnl and 2.5 lsb inl (true for v dd 3.0 v and vref 3.0 v). external filters are required on adc input channels for antialiasing. this ensures that any out-of-band content is not folded into the input signal band. reconfigurable analog resources allow creating complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (single or dual, with 8-bit resolution) pin-to-pin comparator single ended comparators with absol ute (1.3 v) reference or 5-bit dac reference 1.3 v reference (as a system resource) analog blocks are provided in columns of four, which include ct-e (continuous time) and sc-e (switched capacitor) blocks. these devices provide limited functionality type ?e? analog blocks. figure 2. analog system block diagram additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a mac, low voltage detection, and power on rese t. the merits of each system resource are: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. additional digital resources and clocks optimized for csd. support ?rtc? block into digital peripheral logic. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 v reference provides an absolute reference for the analog system, including adcs and dacs. ace01 block array array input configuration aci1[1:0] aci0[1:0] reference generators bandgap agnd ase10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference 10 bit sar adc aci2[3:0] p0[0:7] ace00 ase11 aci1[1:0] aci1[1:0] amuxr amuxl ace11 ace10 [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 5 of 34 psoc device characteristics depending on your psoc device characteristics, the digital and an alog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following tabl e lists the resources available for specific psoc device groups. getting started for in-depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [1] up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [2] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 [1] up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a [1] up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 [1] up to 38 2 8 up to 38 0 4 6 [2] 1 k 16 k cy8c21x45 [1] up to 24 1 4 up to 24 0 4 6 [2] 512 8 k cy8c21x34 [1] up to 28 1 4 up to 28 0 2 4 [2] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [2] 256 4 k cy8c20x34 [1] up to 28 0 0 up to 28 0 0 3 [2,3] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [2,3] up to 2 k up to 32 k notes 1. automotive qualified devices available in this group. 2. limited analog functionality. 3. two analog blocks and one capsense ? block. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 6 of 34 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are adcs, dacs, amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project wit h apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 7 of 34 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the us er module and provide performance specifications. each datasheet de scribes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. these include monitoring address and data bus values, memory locations, and external signals. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 8 of 34 pinouts this psoc device family is available in a variety of packages t hat are listed in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o. ho wever, vss, vdd, and xres are not capable of digital i/o. CY8C22345, cy8c21345 28-pin soic table 2. pin definitions pin no. type pin name description figure 3. pin diagram digital analog 1 i/o i, mr p0[7] integration capacitor for mr 2 i/o i, ml p0[5] integration capacitor for ml 3 i/o i, ml p0[3] 4 i/o i, ml p0[1] 5 i/o i, ml p2[7] to compare column 0 6 i/o ml p2[5] optional adc external vref 7 i/o ml p2[3] 8 i/o ml p2[1] 9 power vss ground connection 10 i/o ml p1[7] i2c serial clock (scl) 11 i/o ml p1[5] i2c serial data (sda) 12 i/o ml p1[3] 13 i/o ml p1[1] i2c serial clock (scl), issp-sclk [4] 14 power vss ground connection 15 i/o mr p1[0] i2c serial clock (scl), issp-sdata [4] 16 i/o mr p1[2] 17 i/o mr p1[4] optional external clock input (ext-clk) 18 i/o mr p1[6] 19 input xres active high pin reset with internal pull down 20 i/o mr p2[0] 21 i/o mr p2[2] 22 i/o mr p2[4] 23 i/o i, mr p2[6] to compare column 1 24 i/o i, mr p0[0] 25 i/o i, mr p0[2] 26 i/o i, mr p0[4] 27 i/o i, mr p0[6] 28 power vdd supply voltage legend : a = analog, i = input, o = output, m=analog mux input, mr= analog mux right input, ml= analog mux left input. ai, mr, p0[7] ai, ml, p0[5] ai, ml, p0[3] ai, ml, p0[1] ai, ml, p2[7] adc_ext_vref, ml, p2[5] ml, p2[3] ml, p2[1] vss i2c scl, ml, p1[7] i2c sda, ml, p1[5] ml, p1[3] i2c scl, ml, p1[1] vss vdd p0[6], mr, ai p0[4], mr, ai p0[2], mr, ai p0[0], mr, ai p2[6], mr, ai p2[4], mr p2[2], mr p2[0], mr xres p1[6], mr p1[4], mr, extclk p1[2], mr p1[0], mr, i2c sdata soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 note 4. issp pin which is not hi-z at por. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 9 of 34 cy8c22545 44-pin tqfp table 3. pin definitions pin no. type pin name description figure 4. pin diagram digital analog 1 i/o ml p2[5] optional adc external vref 2 i/o ml p2[3] 3 i/o ml p2[1] 4 power vdd supply voltage 5 i/o ml p4[5] 6 i/o ml p4[3] 7 i/o ml p4[1] 8 power vss ground connection 9 i/o ml p3[7] 10 i/o ml p3[5] 11 i/o ml p3[3] 12 i/o ml p3[1] 13 i/o ml p1[7] i2c serial clock (scl) 14 i/o ml p1[5] i2c serial data (sda) 15 i/o ml p1[3] 16 i/o ml p1[1] crystal (xtalin), i2c serial clock (scl), tc sclk [4] 17 power vss ground connection 18 i/o mr p1[0] crystal (xtalout), i2c serial data (sda), tc sdata [4 ] 19 i/o mr p1[2] 20 i/o mr p1[4] optional external clock input (extclk) 21 i/o mr p1[6] 22 i/o mr p3[0] 23 i/o mr p3[2] 24 i/o mr p3[4] 25 i/o mr p3[6] 26 input xres active high pin reset with internal pull down 27 i/o mr p4[0] 28 i/o mr p4[2] 29 i/o mr p4[4] 30 power vss ground connection 31 i/o mr p2[0] 32 i/o mr p2[2] 33 i/o mr p2[4] 34 i/o i, mr p2[6] to compare column 1 35 i/o i, mr p0[0] 36 i/o i, mr p0[2] 37 i/o i, mr p0[4] 38 i/o i, mr p0[6] 39 power vdd supply voltage 40 i/o i, mr p0[7] integration capacitor for mr 41 i/o i, ml p0[5] integration capacitor for ml 42 i/o i, ml p0[3] 43 i/o i, ml p0[1] 44 i/o i, ml p2[7] to compare column 0 legend : a = analog, i = input, o = output, m=analog mux input, mr= analog mux right input, ml= analog mux left input. p2[7], ml, ai adc_ext_vref, ml, p2[5] ml, p2[3] ml, p2[1] vdd tqfp 12 13 17 18 14 15 16 1 2 3 4 5 6 7 8 24 23 31 30 29 28 27 26 42 41 39 38 37 36 35 34 p0[1], ml, ai p0[3], ml, ai p0[5], ml, ai p0[7], mr, ai vdd p0[6], mr, ai i2c scl, ml, p1[7] i2c sda, ml, p1[5] p2[0], mr p0[0], mr, ai xres mr, p1[6] ml, p1[3] i2c scl, xtalin, ml, p1[1] i2c sda, xtalout, mr, p1[0] mr, p1[2] extclk, mr, p1[4] vss p2[6], mr, ai p2[4], mr 11 10 9 19 20 21 22 25 32 33 40 43 44 ml, p4[5] ml, p4[3] ml, p4[1] ml, p3[7] ml, p3[5] ml, p3[1] ml, p3[3] mr, p3[0] p3[2], mr p3[4], mr p3[6], mr p4[0], mr p4[2], mr p4[4], mr vss p2[2], mr p0[2], mr, ai p0[4], mr, ai vss [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 10 of 34 registers this section lists the registers of this psoc device family by mapping tables. for detailed register information, refer the psoc programmable system-on chip technical reference manual . register conventions register mapping tables the psoc device has a total register address space of 512 bytes. the register space is also referred to as i/o space and is broken into two parts. the xio bit in the flag register determines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 4. abbreviations convention description rw read and write register or bit(s) r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 11 of 34 table 5. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 # asc10cr0* 80* rw c0 rw prt0ie 01 rw 41 w 81 rw c1 rw prt0gs 02 rw 42 rw 82 rw c2 rw prt0dm2 03 rw 43 # 83 rw c3 rw prt1dr 04 rw 44 # asd11cr0* 84* rw c4 rw prt1ie 05 rw 45 w 85 rw c5 rw prt1gs 06 rw 46 rw 86 rw c6 rw prt1dm2 07 rw 47 # 87 rw c7 rw prt2dr 08 rw 48 # 88 rw pwmvref0 c8 # prt2ie 09 rw 49 w 89 rw pwmvref1 c9 # prt2gs 0a rw 4a rw 8a rw idac_mode ca rw prt2dm2 0b rw 4b # 8b rw pwm_src cb # prt3dr 0c rw 4c # 8c rw ts_cr0 cc rw prt3ie 0d rw 4d w 8d rw ts_cmph cd rw prt3gs 0e rw 4e rw 8e rw ts_cmpl ce rw prt3dm2 0f rw 4f # 8f rw ts_cr1 cf rw prt4dr 10 rw csd0_dr0_l 50 r 90 rw cur pp d0 rw prt4ie 11 rw csd0_dr1_l 51 w 91 rw stk_pp d1 rw prt4gs 12 rw csd0_cnt_l 52 r 92 rw prv pp d2 rw prt4dm2 13 rw csd0_cr0 53 # 93 rw idx_pp d3 rw 14 rw csd0_dr0_h 54 r 94 rw mvr_pp d4 rw 15 rw csd0_dr1_h 55 w 95 rw mvw_pp d5 rw 16 rw csd0_cnt_h 56 r 96 rw i2c 0 _cfg d6 rw 17 rw csd0_cr1 57 rw 97 rw i2c 0 _scr d7 # 18 rw csd1_dr0_l 58 r 98 rw i2c 0 _dr d8 rw 19 rw csd1_dr1_l 59 w 99 rw i2c 0 _mscr d9 # 1a rw csd1_cnt_l 5a r 9a rw int_clr0 da rw 1b rw csd1_cr0 5b # 9b rw int_clr1 db rw 1c rw csd1_dr0_h 5c r 9c rw int_clr 2 dc rw 1d rw csd1_dr1_h 5d w 9d rw int_clr 3 dd rw 1e rw csd1_cnt_h 5e r 9e rw int_msk3 de rw 1f rw csd_cr1 5f rw 9f rw int_msk 2 df rw dbc00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw a1 int_msk1 e1 rw dbc00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rw dbc01dr1 25 w asy_cr 65 # a5 dec_dl e5 rw dbc01dr2 26 rw cmp_cr1 66 rw a6 dec _cr0* e6 rw dbc01cr0 27 # 67 rw a7 dec_cr1* e7 rw dcc02dr0 28 # adc0_cr 68 # a8 w mul 0 _x e8 w dcc02dr1 29 w adc1_cr 69 # a9 w mul 0 _y e9 w dcc02dr2 2a rw sadc_dh 6a rw aa r mul 0 _dh ea r dcc02cr0 2b # sadc_dl 6b rw ab r mul 0 _dl eb r dcc03dr0 2c # tmp_dr0 6c rw ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rw rdi0ri b0 rw cpu a f0 # dbc10dr1 31 w 71 rw rdi0syn b1 rw cpu_t1 f1 # dbc10dr2 32 rw acb00cr1* 72* rw rdi0is b2 rw cpu_t2 f2 # dbc10cr0 33 # acb00cr2* 73* rw rdi0lt0 b3 rw cpu_x f3 # dbc11dr0 34 # 74 rw rdi0lt1 b4 rw cpu pcl f4 # dbc11dr1 35 w 75 rw rdi0ro0 b5 rw cpu_pch f5 # dbc11dr2 36 rw acb01cr1* 76* rw rdi0ro1 b6 rw cpu_sp f6 # dbc11cr0 37 # acb01cr2* 77* rw rdi0dsm b7 rw cpu_f f7 i dcc12dr0 38 # 78 rw rdi1ri b8 rw cpu_tst0 f8 rw dcc12dr1 39 w 79 rw rdi1syn b9 rw cpu_tst1 f9 rw dcc12dr2 3a rw 7a rw rdi1is ba rw cpu_tst2 fa rw dcc12cr0 3b # 7b rw rdi1lt0 bb rw cpu tst3 fb # dcc13dr0 3c # 7c rw rdi1lt1 bc rw dac1_d fc rw dcc13dr1 3d w 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rw rdi1dsm bf rw cpu_scr0 ff # shaded fields are reserved and must not be accessed. # access is bit specific. * has a different meaning. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 12 of 34 table 6. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 0 rw 40 rw asc10cr0* 80* rw c0 rw prt0dm1 1 rw 41 rw 81 rw c1 rw prt0ic0 2 rw 42 rw 82 rw c2 rw prt0ic1 3 rw 43 83 rw c3 rw prt1dm0 4 rw 44 rw asd11cr0* 84* rw c4 rw prt1dm1 5 rw 45 rw 85 rw c5 rw prt1ic0 6 rw 46 rw 86 rw c6 rw prt1ic1 7 rw 47 87 rw c7 rw prt2dm0 8 rw 48 rw 88 rw c8 # prt2dm1 9 rw 49 rw 89 rw c9 rw prt2ic0 0a rw 4a rw 8a rw ca rw prt2ic1 0b rw 4b 8b rw cb rw prt3dm0 0c rw 4c rw 8c rw cc # prt3dm1 0d rw 4d rw 8d rw cd rw prt3ic0 0e rw 4e rw 8e rw ce rw prt3ic1 0f rw 4f 8f rw cf rw prt4dm0 10 rw cmp0cr1 50 rw 90 rw gdi_o_in d0 rw prt4dm1 11 rw cmp0cr2 51 rw 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 rw 92 rw gdi_o_ou d2 rw prt4ic1 13 rw vdac50cr0 53 rw 93 rw gdi_e_ou d3 rw 14 rw cmp1cr1 54 rw 94 rw d4 rw 15 rw cmp1cr2 55 rw 95 rw d5 rw 16 rw 56 rw 96 rw d6 rw 17 rw vdac51cr0 57 rw 97 rw d7 rw 18 rw cscmpcr0 58 # 98 rw mux_cr0 d8 rw 19 rw cscmpgoen 59 rw 99 rw mux_cr1 d9 rw 1a rw cslutcr0 5a rw 9a rw mux_cr2 da rw 1b rw cmpcolmux 5b rw 9b rw mux_cr3 db rw 1c rw cmppwmcr 5c rw 9c rw dac_cr1# dc rw 1d rw cmpfltcr 5d rw 9d rw osc_go_en dd rw 1e rw cmpclk1 5e rw 9e rw osc_cr4 de rw 1f rw cmpclk0 5f rw 9f rw osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 r dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr* e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr* e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw v2bg_tr e7 rw dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 w dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 w dcc02ou 2a rw 6a rw sadc_cr2 aa rw bdg_tr ea rw dbc02cr1 2b rw clk_cr3 6b rw sadc_cr3tri m ab rw eco_tr eb w dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_ad ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae rw mux_cr6 ee rw dbc03cr1 2f rw tmp_dr3 6f rw af rw mux_cr7 ef rw dbc10fn 30 rw 70 rw rdi0ri b0 rw cpu a f0 # dbc10in 31 rw 71 rw rdi0syn b1 rw cpu_t1 f1 # dbc10ou 32 rw acb00cr1* 72 rw rdi0is b2 rw cpu_t2 f2 # dbc10cr1 33 rw acb00cr2* 73 rw rdi0lt0 b3 rw cpu_x f3 # dbc11fn 34 rw 74 rw rdi0lt1 b4 rw cpu_pcl f4 # dbc11in 35 rw 75 rw rdi0ro0 b5 rw cpu_pch f5 # dbc11ou 36 rw acb01cr1* 76* rw rdi0ro1 b6 rw cpu_sp f6 # dbc11cr1 37 rw acb01cr2* 77* rw rdi0dsm b7 rw cpu_f f7 i dcc12fn 38 rw 78 rw rdi1ri b8 rw fls_pr0 f8 rw dcc12in 39 rw 79 rw rdi1syn b9 rw fls tr f9 w dcc12ou 3a rw 7a rw rdi1is ba rw fls_pr1 fa rw dbc12cr1 3b rw 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rw rdi1lt1 bc rw fac_cr0 fc sw dcc13in 3d rw 7d rw rdi1ro0 bd rw dac_cr0# fd rw dcc13ou 3e rw 7e rw rdi1ro1 be rw cpu_scr1 fe # dbc13cr1 3f rw 7f rw rdi1dsm bf rw cpu_scr0 ff # shaded fields are reserved and must not be accessed. # access is bit specific. * has a different meaning. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 13 of 34 electrical specifications this section presents the dc and ac electrical specifications of this psoc device family. for the latest electrical specificati ons, check the most recent data sheet by visiting http://www.cypress.com. specifications are valid for -40c t a 85c and t j 100c, except where noted . specifications for devi ces running at greater than 12 mhz are valid for -40c t a 70c and t j 82c. figure 5. voltage versus operating frequency 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o pe r a t i n g r e gi o n [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 14 of 34 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 c higher storage tempera- tures reduce data retention time t baketemp bake temperature - 125 see package label o c t baketime bake time see package label - 72 hours t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tristate vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma table 8. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see table 29 on page 26. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 15 of 34 dc electrical characteristics dc chip level specifications ta b l e 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c, and are for design guidance only, unless specified otherwise. dc gpio specifications ta b l e 1 0 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only, unless otherwise specified. table 9. dc chip level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see table 16 on page 17 i dd supply current ? 7 12 ma conditions are vdd = 5.0 v, 25c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz vc2 = 93.75 khz vc3 = 93.75 khz i dd3 supply current ? 4 7 ma conditions are vdd = 3.3 v t a = 25c, cpu = 3 mhz 48 mhz = disabled vc1 = 1.5 mhz, vc2 = 93.75 khz vc3 = 93.75 khz i sb sleep (mode) current with por, lvd, sleep timer, and wdt [5] ? 3 6.5 a conditions are with internal slow speed oscillator, vdd = 3.3 v -40c <= t a <= 55c i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature [5] ? 4 25 a conditions are with internal slow speed oscillator, vdd = 3.3 v 55c < t a <= 85c i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal [5] ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3 v, -40c <= t a <= 55c i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature [5] ? 5 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3 v, 55c < t a <= 85c v ref reference voltage (bandgap) 1.275 1.3 1.325 v trimmed for appropriate vdd note 5. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this must be compare d with devices that have similar functions enabled. table 10. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v i oh = 10 ma, vdd = 4.75 to 5.25 v (80 ma maximum combined i oh budget) v ol low output level ? ? 0.75 v i ol = 25 ma, vdd = 4.75 to 5.25 v (100 ma maximum combined i ol budget) i oh high level source current 10 ? ? ma v oh = vdd-1.0 v, see the limitations of the total current in the note for v oh. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 16 of 34 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and te mperature ranges: 4.75 v to 5 .25 v and -40 c t a 85 c, 3.0 v to 3.6 v and -40 c t a 85 c respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc low power comparator specifications ta b l e 1 3 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, 3.0 v to 3.6 v and -40 c t a 85 c respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c table 10. dc gpio specifications (continued) symbol description min typ max units notes table 11. 5 v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa [6] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c v cmoa common mode voltage range 0.0 ? vdd - 1 v note 6. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25c; 50 na over temperat ure. use port 0 pins 1-7 for the lowest leakage of 200 na. table 12. 3.3 v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa [6] input leakage current (port 0 anal og pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0 ? vdd ? 1 v table 13. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 17 of 34 sar10 adc dc specifications ta b l e 1 4 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc analog mux bus specifications ta b l e 1 5 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 6 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 14. sar10 adc dc specifications symbol description min typ max units notes v adcvref reference voltage at pin p2[5] when configured as adc reference voltage 3.0 ? 5.25 v when v ref is buffered inside adc, the voltage level at p2[5] (when configured as adc reference voltage) must be always maintained to be at least 300 mv less than the chip supply voltage level on vdd pin. (v adcvref < vdd) i adcvref current when p2[5] is configured as adc v ref - ? 0.5 ma disables the internal voltage reference buffer inl at 10 bits integral nonlinearity -2.5 ?2.5lsbfor v dd 3.0 v and vref 3.0 v -5.0 ?5.0lsbfor v dd < 3.0 v or vref < 3.0 v dnl at 10 bits differential nonlinearity -1.5 ?1.5lsbfor v dd 3.0 v and vref 3.0 v -4.0 ?4.0lsbfor v dd < 3.0 v or vref < 3.0 v sps sample per second ? ? 150 ksps resolution 10 bits table 15. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 vdd 3.00 r gnd resistance of initialization switch to gnd ? ? 800 table 16. dc por and lvd specifications symbol description min typ max units notes v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 01b porlev[1:0] = 10b ?2.82 4.55 2.95 4.70 v v vdd must be greater than or equal to 3.0 v during startup, reset from the xres pin, or reset from watchdog. v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.95 3.06 4.37 4.50 4.62 4.71 3.02 3.13 4.48 4.64 4.73 4.81 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 18 of 34 dc programming specifications ta b l e 1 7 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 17. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) [8] 50,000 ? ? ? erase/write cycles per block flash ent flash endurance (total) [7] 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years note 7. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operatio ns on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles ea ch, or 36x4 blocks of 12,500 maxi mum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 8. the 50,000 cycle flash endurance per block is guaranteed only if the flash operat es within one voltage range. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v 9. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections.the i 2 c gpio pins also meet the above specs. table 18. dc i 2 c specifications parameter description min typ max units notes v ili2c [9] input low level ? ? 0.3 v dd v 3.0 v v dd 3.6 v ? ? 0.25 v dd v 4.75 v v dd 5.25 v v ihi2c [9] input high level 0.7 v dd ? ? v 3.0 v v dd 5.25 v [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 19 of 34 ac electrical characteristics ac chip level specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and te mperature ranges: 4.75 v to 5 .25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 19. 5 v and 3.3 v ac chip-level specifications symbol description min min(%) typ max max(%) units notes f imo24 internal main oscillator frequency for 24 mhz 22.8 ? 24 25.2 [10,11 ,12] ? mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 5 on page 13. slimo mode = 0 < 85 f imo6 internal main oscillator frequency for 6 mhz 5.5 8 6 6.5 [10,11, 12] 8 mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 5 on page 13. slimo mode = 0 < 85. f cpu1 cpu frequency (5 v nominal) 0.089 ? 24 24.6 [10,11 ] ? mhz 24 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.089 ? 12 12.3 [11,12 ] ? mhz slimo mode = 0. f blk5 digital psoc block frequency 0 (5 v nominal) 0 ? 48 49.2 [10,11 ,13] ? mhz refer to table 23 on page 21. f blk33 digital psoc block frequency (3.3 v nominal) 0 ? 24 24.6 [11,13 ] ? mhz f 32k1 internal low speed oscillator frequency 15 ? 32 85 ? khz f 32ku untrimmed internal low speed oscillator frequency 5 ? ? 100 ? khz the ilo is not adjusted with the factory trim values until after the cpu starts running. see the ?system resets? section in the technical reference manual. t xrst external reset pulse width 10 ? ? ? ? s dc24m 24 mhz duty cycle 40 ?5060 ?% dc ilo internal low speed oscillator duty cycle 20 ?5080 ?% f out48m 48 mhz output frequency 46.8 ? 48.0 49.2 ?mhz trimmed. utlizing factory trim values. f max maximum frequency of signal on row input or row output ? ? ? 12.3 ? mhz sr powerup power supply slew rate ? ? ? 250 ? v/ms vdd slew rate during power up. t powerup time from end of por to cpu executing code ? ? ? 100 ? ms tjit_imo [14] 24 mhz imo cycle-to-cycle jitter (rms) ? ? 200 700 ? ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? ? 300 900 ? ps n = 32 24 mhz imo period jitter (rms) ? ? 100 400 ? ps tjit_pll [14] 24 mhz imo cycle-to-cycle jitter (rms) ? ? 200 800 ? ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? ? 300 1200 ? ps n = 32 24 mhz imo period jitter (rms) ? ? 100 700 ? ps notes 10. valid only for 4.75 v < vdd < 5.25 v. 11. accuracy derived from internal main oscillator with appropriate trim for vdd range. 12. 3.0 v < vdd < 3.6 v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimming for operation at 3.3 v. 13. refer to the individual user module data sheets fo r information on maximum frequencies for user modules. 14. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timi ng products ? an5054 for more information. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 20 of 34 ac gpio specifications ta b l e 2 0 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. figure 6. gpio timing diagram ac operational amplifier specifications ta b l e 2 1 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. ac low power comparator specifications ta b l e 2 2 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical para meters apply to 5 v at 25 c and are for design guidance only. table 20. 5 v and 3.3 v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25 v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25 v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 5.25 v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 5.25 v, 10% - 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 21. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv 100 ns vdd 3.0 v table 22. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 21 of 34 ac digital block specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and te mperature ranges: 4.75 v to 5 .25 v and -40 c t a 85 c or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v, at 25 c and are for design guidance only. table 23. ac digital block specifications function description min typ max units notes all functions block input clock frequency vdd 4.75 v ? ? 50.4 [16] mhz vdd < 4.75 v ? ? 25.2 [16] mhz timer input clock frequency no capture, vdd 4.75 v ? ? 50.4 [16] mhz no capture, vdd < 4.75 v ? ? 25.2 [16] mhz with capture ? ? 25.2 [16] mhz capture pulse width 50 [15] ??ns counter input clock frequency no enable input, vdd 4.75 v ? ? 50.4 [16] mhz no enable input, vdd < 4.75 v ? ? 25.2 [16] mhz with enable input ? ? 25.2 [16] mhz enable input pulse width 50 [15] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [15] ??ns disable mode 50 [15] ??ns input clock frequency vdd 4.75 v ? ? 50.4 [16] mhz vdd < 4.75 v ? ? 25.2 [16] mhz crcprs (prs mode) input clock frequency vdd 4.75 v ? ? 50.4 [16] mhz vdd < 4.75 v ? ? 25.2 [16] mhz crcprs (crc mode) input clock frequency ? ? 25.2 [16] mhz spim input clock frequency ? ? 8.4 [16] mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.2 [16] mhz the input clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [15] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. vdd 4.75 v, 2 stop bits ? ? 50.4 [16] mhz vdd 4.75 v, 1 stop bit ? ? 25.2 [16] mhz vdd < 4.75 v ? ? 25.2 [16] mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. vdd 4.75 v, 2 stop bits ? ? 50.4 [16] mhz vdd 4.75 v, 1 stop bit ? ? 25.2 [16] mhz vdd < 4.75 v ? ? 25.2 [16] mhz notes 15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). 16. accuracy derived from imo with appropriate trim for v dd range. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 22 of 34 ac external clock specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and te mperature ranges: 4.75 v to 5 .25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. sar10 adc ac specifications ta b l e 2 6 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 24. 5 v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 25. 3.3 v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 26. sar10 adc ac specifications symbol description min typ max units notes freq 3 input clock frequency 3 v ? ?2.7mhz freq 5 input clock frequency 5 v ? ?2.7mhz [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 23 of 34 ac programming specifications ta b l e 2 7 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, or 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v, or 3.3 v at 25 c and are for design guidance only. table 27. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz f sclk3 frequency of sclk3 0 ? 6 mhz v dd < 3.6 v t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 55 ns 3.6 < vdd; at 30 pf load t dsclk3 data out delay from falling edge of sclk ? ? 65 ns 3.0 vdd 3.6; at 30 pf load t eraseall flash erase time (bulk) ? 40 ? ns t program_hot flash block erase + flash block write time ? ? 100 ms t program_cold flash block erase + flash block write time ? ? 200 ms [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 24 of 34 ac i 2 c specifications ta b l e 2 8 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and -40 c t a 85 c, and 3.0 v to 3.6 v and -40 c t a 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. figure 7. definition for timing for fast/standard mode on the i 2 c bus table 28. ac characteristics of the i 2 c sda and scl pins for vdd 3.0 v symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [17] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter ? ?050ns note 17. a fast-mode i2c-bus device may be used in a standard-mode i2c-bus system, but the requirement t sudati2c 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 25 of 34 packaging information figure 8. 28-pin soic figure 9. 44-pin tqfp 51-85026 *f 51-85064 *e [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 26 of 34 thermal impedances solder reflow specifications ta b l e 3 0 shows the solder reflow temperature limits that must not be exceeded. ordering information the following table lists the key package features and ordering codes of this psoc device family. ordering code definitions table 29. thermal impedances per package package typical ja [19] 28 soic 68c/w 44 tqfp 61c/w table 30. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 28 soic 260 c 30 seconds 44 tqfp 260 c 30 seconds table 31. psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital i/o pins analog inputs analog outputs xres pin 28 soic cy8c21345-24sxi 8 512b -40c to +85c 4 6 24 24 [18] 0 y 28 soic (tape and reel) cy8c21345-24sxit 8 512b -40c to +85c 4 6 24 24 [18] 0 y 28 soic CY8C22345-24sxi 16 1k -40c to +85c 8 6 24 24 [18] 0 y 28 soic (tape and reel) CY8C22345-24sxit 16 1k -40c to +85c 8 6 24 24 [18] 0 y 44 tqfp cy8c22545-24axi 16 1k -40c to +85 c 8 6 38 38 [18] 0 y 44 tqfp (tape and reel) cy8c22545-24axit 16 1k -40c to +85 c 8 6 38 38 [18] 0 y note 18. ten direct inputs. cy 8 c 2x xxx-spxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/ltx = qfn pb-free ax = tqfp pb-free cpu speed: 24 mhz part number family code (21, 22) technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 27 of 34 acronyms acronyms used ta b l e 3 2 lists the acronyms that are used in this document. reference documents cy8c22x45 and cy8c21345 psoc? programmable system-on-chip? technical reference manual (trm) (001-48461) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) notes 19. t j = t a + power x ja table 32. acronyms used in this datasheet acronym description acronym description ac alternating current mac multiply-accumulate adc analog-to-digital converter mcu microcontroller unit api application programming interfac e mips million instructions per second cmos complementary metal oxide semiconductor pcb printed circuit board cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop csd capsense sigma delta por power on reset ct continuous time ppor precision power on reset dac digital-to-analog converter prs pseudo-random sequence dc direct current psoc ? programmable system-on-chip dnl differential nonlinearity pwm pulse width modulator eco external crystal oscillator qfn quad flat no leads eeprom electrically erasable programmable read-only memory rtc real time clock fsk frequency-shift keying sar successive approximation gpio general-purpose i/o sc switched capacitor i/o input/output slimo slow imo ice in-circuit emulator soic small-outline integrated circuit ide integrated development environment spi? serial peripheral interface idac current dac sram static random access memory ilo internal low speed oscillator srom supervisory read only memory imo internal main oscillator ssop shrink small-outline package inl integral nonlinearity tqfp thin quad flat pack irda infrared data association uart universal asynchronous reciever / transmitter issp in-system serial programming usb universal serial bus lpc low power comparator wdt watchdog timer lsb least-significant bit xres external reset lvd low voltage detect [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 28 of 34 document conventions units of measure ta b l e 3 3 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 33. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes mv millivolts c degree celsius na nanoampere khz kilohertz ns nanosecond k kilohm w ohm lsb least significant bit % percent mhz megahertz pf picofarad a microampere ps picosecond s microsecond sps samples per second v microvolts pa pikoampere ma milliampere v volts mm millimeter w microwatts ms millisecond w watt glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for progr ammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 29 of 34 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fixed fr equency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. glossary (continued) [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 30 of 34 digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connec t low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses vdd and provides an interrupt to the system when vdd falls below a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. glossary (continued) [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 31 of 34 master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is below a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. glossary (continued) [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 32 of 34 serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device that sequentially shif ts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged until it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory . the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three stat es: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
cy8c21345 CY8C22345, cy8c22545 document number: 001-43084 rev. *m page 33 of 34 document history page document title: cy8c21345, CY8C22345, cy8c22545 psoc ? programmable system-on-chip document number: 001-43084 revision ecn orig. of change submission date description of change ** 2251907 pmp/aesa see ec n new data sheet *a 2506377 eij/aesa see ecn changed data sheet stat us to ?preliminary?. changed part numbers to cy8c22x45. updated data sheet template. added 56-pin ocd information. added: ?you must put filters on intended adc input channels for anti-aliasing. this ensures that any out-of-band content is not folded into the input signal band." to section analog system on page 4. corrected minimum electro static discharge voltage in table 7 on page 14. *b 2558750 pmp/aesa 08/28/2008 updated features on page 1, psoc core on page 3, analog system on page 4. changed dbb to dbc, and dcb to dcc in register tables table 5 on page 11 and table 6 on page 12. removed inl at 8 bit reference in table 14 on page 17. changed idd3 value table 16 on page 17 typ:3.3 ma, max 6 ma added ?3.0 v < vdd < 3.6 v and -40c < t a < 85c, imo can guarantee 5% accuracy only? to table 19 on page 19. updated data sheet template. *c 2606793 nuq/aesa 11/19/2008 updated data sheet status to ?final?. updated block diagram on page 1. removed cy8c22045 56-pin ocd information. added part numbers cy8c21345, CY8C22345, and cy8c22545. for more details, see cdt 31271. *d 2615697 pmp/aesa 12/03/2008 confirmed CY8C22345 and cy8c21345 have same pinout on page 8. confirmed that imo has 5% accuracy in table 19 on page 19. *e 2631733 pmp/pyrs 01/07/2009 updated table 16. sar10 adc dc specifications and table 29 ac programming specifications. title changed to ?cy8c21345, CY8C22345, cy8c22545 psoc? programmable system-on-chip?? *f 2648800 jhu/aesa 01/28/2009 updated inl, dnl information in table 14 on page 17, development tools on page 6, and t dsclk parameter in table 27 on page 23. *g 2658078 hmi/aesa 02/11/2 009 updated section features on page 1. *h 2667311 jhu/aesa 03/16/2009 added parameter ?f 32ku ? and added min% and max % to parameter ?f imo6 ? in table 19 on page 19, according to updated slimo spec. *i 2748976 jzhu/pyrs 08/06/2009 updated f 32k1 max rating in table 19 on page 19. *j 2786560 jzhu 10/23/2009 added dc ilo , t eraseall , t program_hot , t program_cold , sr powerup , i oh , and i ol parameters. added tape and reel parts in ordering information table *k 2901653 njf 03/30/2010 updated psoc designer software subsystems . added t baketemp and t baketime parameters in absolute maximum ratings modified note 6 on page 17. added f out48m parameter in 5 v and 3.3 v ac chip-level specifications . removed ac analog mux bus specifications. updated ordering code definitions . updated links in sales, solutions, and legal information . *l 3114978 njf 12/19/10 added dc i 2 c specifications. added tjit_imo specification, removed existing jitter specifications. updated dc programming specifications. updated ac digital block specifications. updated i 2 c timing diagram. added solder reflow peak temperature table. updated units of measure, acronyms, glossary, and references sections. [+] feedback
document number: 001-43084 rev. *m revised may 23, 2011 page 34 of 34 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21345 CY8C22345, cy8c22545 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 *m 3231771 bobh/ecu 04/18/11 updated analog inputs column in table 31 on page 26 and included reference to note 18. updated the following sections: getting started , development tools , and designing with psoc designer as all the system level designs have been de-emphasized. updated table 30, ?solder reflow specifications,? on page 26. updated package diagrams: 51-85026 to *f 51-85064 to *e document title: cy8c21345, CY8C22345, cy8c22545 psoc ? programmable system-on-chip document number: 001-43084 [+] feedback

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